An LDMOS (Laterally Diffused MOS) transistor having a structure in which an impurity layer near a drain is diffused laterally has heretofore been known. Studies to achieve an increase in breakdown voltage of the LDMOS transistor and a reduction in on-resistance thereof have been done.
There has been disclosed in, for example, a Non-Patent Literature 1, a structure of an LDMOS transistor 850 in which a P− layer 803 is disposed below an N− drift layer (hereinafter, an N− layer) 801 as illustrated in FIG. 30. According to this structure, a parasitic capacitance is generated between the P− layer 803 and the N− layer 801 and an electric charge is accumulated in the parasitic capacitance. Therefore, a depletion layer is formed in the N− layer 801. Thus, it is possible to relax a surface electric field of the N− layer 801 (i.e., obtain Reduced Surface Field: RESURF effect) and increase a drain breakdown voltage (i.e., OFF-BVdss) in an off state.